#Dajiang Liu

Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory

RAPID Team , 清华大学

Affine transformations for communication and reconfiguration optimization of loops on CGRAs

RAPID Team , 清华大学

Polyhedral model based mapping optimization of loop nests for CGRAs

RAPID Team , 清华大学

Design and Implementation of an SD Interface to Multiple-Target Interface Bridge

RAPID Team , 清华大学

Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures

RAPID Team , 清华大学

DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach

RAPID Team , 清华大学

Joint Affine Transformation and Loop Pipelining for Mapping Nested Loop on CGRAs

RAPID Team , 清华大学

Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures

RAPID Team , 清华大学

LabXing 上可以免费创建课题组网站