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#Leibo Liu
Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory
RAPID Team , 清华大学
Energy-aware loops mapping on multi-vdd CGRAs without performance degradation
RAPID Team , 清华大学
Affine transformations for communication and reconfiguration optimization of loops on CGRAs
RAPID Team , 清华大学
Polyhedral model based mapping optimization of loop nests for CGRAs
RAPID Team , 清华大学
Design and Implementation of an SD Interface to Multiple-Target Interface Bridge
RAPID Team , 清华大学
Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures
RAPID Team , 清华大学
DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach
RAPID Team , 清华大学
Joint Affine Transformation and Loop Pipelining for Mapping Nested Loop on CGRAs
RAPID Team , 清华大学
Template-based compilation for coarse-grained reconfigurable processor
RAPID Team , 清华大学
Performance evaluation modeling for reconfigurable processor
RAPID Team , 清华大学
Compiler framework for reconfigurable computing system
RAPID Team , 清华大学
A data-flow graph generation algorithm for a coarse-grained reconfigurable processor
RAPID Team , 清华大学
A mapping algorithm for embedded coarse-grained reconfigurable processor
RAPID Team , 清华大学
An inductive-coupling interconnected application-specific 3D NoC design
RAPID Team , 清华大学
Optimizing buffer usage for Networks-on-Chip design
RAPID Team , 清华大学
Battery aware tasks allocating algorithm for multi-battery operated system
RAPID Team , 清华大学
Map-reduce inspired loop parallelization on CGRA
RAPID Team , 清华大学
Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms
RAPID Team , 清华大学
RNA: A Reconfigurable Architecture for Hardware Neural Acceleration
RAPID Team , 清华大学
Key techniques of recon gurable computing processor
RAPID Team , 清华大学
A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation
RAPID Team , 清华大学
Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures
RAPID Team , 清华大学
Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures
RAPID Team , 清华大学
Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures
RAPID Team , 清华大学